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Engineers moving into multi-die, chiplet-based system design often run into a real knowledge gap. A specialist in one discipline — electrical, thermal, mechanical, or reliability — may lack working fluency in the others, and most available references survey a single packaging technology in isolation rather than connecting architecture selection through to a shipped, qualified part.
This handbook closes that gap. It is organized as a decision path — select, design, build, qualify, analyze failures, and test — so a reader can follow a single packaging decision from the moment an architecture is chosen through the moment a shipped part is qualified. It is also built to be worked rather than simply read: every chapter carries fully worked numerical examples, with every variable defined and every unit tracked, plus end-of-chapter practice problems with boxed final answers.
Inside, you will:
Understand why chiplet-based heterogeneous integration has become a mainstream engineering strategy, and how to weigh package families against cost, performance, and integration-density requirements
Follow first-principles derivations of package electrical parasitics and thermal-resistance networks, then apply them to real package geometries
Work through wafer-level/fan-out packaging, silicon-interposer/bridge 2.5D integration, and through-silicon-via/hybrid-bonding 3D die stacking with real design-rule detail
Apply a partitioning framework for deciding where to cut a monolithic design into chiplets, driven by yield-and-cost economics
Design package substrates, interconnect, signal/power integrity, and thermal/thermomechanical margins for multi-die packages
Build a reliability qualification test plan, interpret reliability data, and carry a failure through root-cause analysis
Apply a known-good-die test strategy and a cost-modeled package-selection framework, closing with a full worked, multi-chiplet case study
Key topics covered include: package evolution and taxonomy; materials, electrical, and thermal fundamentals; wafer-level and fan-out packaging; silicon-interposer and bridge-based 2.5D integration; through-silicon-via and hybrid-bonding 3D die stacking; chiplet partitioning and die-to-die interconnect standards; system-in-package and multi-chip module design; substrate and interconnect design; signal and power integrity; thermal and thermomechanical design; manufacturing processes; reliability qualification; failure analysis; known-good-die test strategy; package selection and cost modeling; and emerging directions in co-packaged optics and glass-core substrates.
This handbook is written for senior undergraduate and graduate engineering students building a foundation in advanced packaging; packaging, mechanical, materials, electrical, thermal, and reliability engineers who need working depth outside their home discipline; product, test, quality, and manufacturing engineers translating packaging choices into yield and cost outcomes; technical managers who approve packaging decisions without necessarily deriving every equation themselves; and researchers who need a rigorous, currently sourced reference point.
Open this handbook and begin tracing a real packaging decision — from architecture selection through qualification — with derivations you can check and design rules you can apply.
